`timescale 1ps / 1ps
module Ext(input ExtOp,
           input [15:0] in,
           output reg[31:0]out);
    
    integer i;
    always @(*) begin
        if (ExtOp) begin
            out[15:0] = in;
            for (i = 31;i >= 16;i = i-1) begin
                out[i] = in[15];
            end
                
        end
        else begin
            out       = 0;
            out[15:0] = in;
        end
    end
    
endmodule
